Synopsys and tsmc drive chip innovation with development of broadest ip portfolio on tsmc n4p process

Mountain view, calif., oct. 27, 2021 /prnewswire/ -- highlights from this announcement: designware interface ip for the most widely used protocols delivers the required high bandwidth and low latency for efficient data connectivity in compute-intensive designs on tsmc n4p process designware foundation ip offers high-speed, area-optimized and low-power embedded memories, logic libraries, gpios and tcams broad ip portfolio on tsmc's n4p process complements synopsys' certified digital and custom design solutions for the process, accelerating time to silicon success   to facilitate chip innovation and enable designers to quickly achieve silicon success of complex high-performance computing (hpc) and mobile socs, synopsys, inc. (nasdaq: snps) today announced a collaboration with tsmc to develop a broad portfolio of synopsys designware® interface and foundation ip on the tsmc n4p process.
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