Synopsys and tsmc usher in angstrom-scale designs with certified eda flows on advanced tsmc a16 and n2p processes

Ai-driven digital and analog flows, multi-die innovations, and broad ip portfolio deliver unmatched performance, power  and area advantages highlights digital and analog design flows on tsmc a16™ and n2p deliver optimized performance and rapid analog design migration, enabled by synopsys.ai early collaboration on tsmc a14 process underway for synopsys eda flows development collaboration on 3dblox and tsmc's cowos® technologies for 5.5x reticle size packages, speeds integration of 3d stacked dies in next-generation ai chips broad portfolio of synopsys foundation and interface ip provides the lowest power on tsmc's n2/n2p processes industry's most complete ip solutions for leading-edge standards, including hbm4, 1.6t ethernet, ucie, pcie 7.0, and ualink, enable high-bandwidth interfaces in data-intensive heterogeneous socs sunnyvale, calif. , april 23, 2025 /prnewswire/ -- synopsys, inc. (nasdaq: snps) announced today its ongoing close collaboration with tsmc to deliver robust eda and ip solutions for tsmc's most advanced processes and advanced packaging technologies to accelerate ai chip design and 3d multi-die design innovation.
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